Mustafa Kanchwala
Digital ASIC Designer · Computer Architecture · PhD Candidate, University of Toronto
Hi! I'm a digital ASIC and computer architecture engineer focused on energy-efficient hardware for AI, signal processing, and edge-intelligence systems. I am a PhD candidate in the Intelligent Sensory Microsystems Lab at the University of Toronto, advised by Prof. Roman Genov.
Over five years of my PhD, I have worked across the full chip-design stack: defining system architecture, translating algorithms into microarchitecture, writing synthesizable RTL, integrating digital subsystems into mixed-signal SoCs, closing timing, validating on FPGA, and supporting silicon bring-up. Across four 65 nm CMOS tape-outs, I have contributed to streaming data paths, DSP/filtering pipelines, adaptive control, feature extraction, ML inference, packetization, and hardware/software validation.
My strengths are in RTL design, microarchitecture, SoC integration, and ML accelerator design. I enjoy working at the boundary between algorithms and hardware — training and evaluating ML models, understanding their compute and memory requirements, and mapping them into efficient digital architectures for real-time inference. Results published at IEEE ISSCC, VLSI Technology and Circuits, IEEE TBioCAS, and IEEE BioCAS. Recipient of the NSERC PGS-D Scholarship for 2023–2025.
News
Research Highlights
Spatially Zooming ADC Control Logic
Designed low-power digital control logic for adaptive dynamic-range operation of an energy-efficient zooming ADC front-end, featuring three incremental resolution modes for a multi-channel neural sensing SoC. Click to view the same detailed project write-up from the Projects tab.
Event-Driven Neural Interface SoC
Designed RTL for a scalable mode-switching controller for an inverter-based AFE, a band-pass digital filter, and an area-efficient ML accelerator for event-driven neural signal detection and processing. Enabled best-in-class 10 nW/channel event-driven operation.
Split-Inference Edge-AI SoC
Led RTL system design and top-level digital integration for a split-inference AI SoC, owning feature extraction, classification, ML processing, digital filtering, control logic, and SoC data-path integration. Accepted at IEEE VLSI 2026.
Edge AI Accelerator SoC
Designed an Edge AI accelerator and data-path blocks, including a configurable processing element, adaptive AFE mode-switching controller, DSP/filtering pipeline, and data packetization logic. Led digital integration with a custom pad-frame and optimized the data path for efficient wireless transceiver operation.
Selected Publications
Silicon Tape-Outs
Spatially Zooming ADC Control Logic
Designed low-power digital control logic for adaptive dynamic-range operation of an energy-efficient zooming ADC front-end, featuring three incremental resolution modes for a multi-channel neural sensing SoC. Led microarchitecture, RTL, simulation, synthesis, block integration, and post-silicon validation.
Event-Driven Neural Interface SoC
Designed RTL for a scalable mode-switching controller for an inverter-based AFE, a band-pass digital filter, and an area-efficient ML accelerator for event-driven neural signal detection and processing. Enabled best-in-class 10 nW/channel event-driven operation. Published at IEEE ISSCC 2025.
Split-Inference Edge-AI SoC
Led RTL system design and top-level digital integration for a split-inference AI SoC, owning feature extraction, classification, ML processing, digital filtering, control logic, and SoC data-path integration. Designed low-power accelerator/control blocks to reduce on-chip compute and off-chip communication energy while preserving real-time inference behavior. Accepted at IEEE VLSI 2026.
Edge AI Accelerator SoC
Designed an Edge AI accelerator and data-path blocks, including a configurable processing element, adaptive AFE mode-switching controller, DSP/filtering pipeline, and data packetization logic for edge-inference SoC operation. Led digital integration with a custom pad-frame and optimized the data path for efficient wireless transceiver operation.
FPGA & Platform Projects
Split-Inference SoC Real-Time Validation
Integrated a split-inference Edge AI SoC with a Zynq-based neural recording/stimulation platform, enabling real-time neural-data streaming into the chip's on-chip spike-classification engine and retrieval of inference outputs. Designed Verilog interface/data-path logic and custom PCB for modular chip-to-platform validation; validated the workflow from model pre-training to real-time on-chip classification.
Reconfigurable Neural Recording & Stimulation Platform
Developed a Zynq-7030 FPGA-based closed-loop validation platform for neural recording and stimulation, connecting custom front-end PCBs, neural interface ASICs, embedded Linux control, and Python-based visualization. Designed RTL streaming pipelines with FIFO buffering, packet formatting, AXI/APB control, and embedded Linux data streaming for real-time acquisition and closed-loop intervention. Published at IEEE BioCAS 2025.
NVDLA Accelerator Core with RISC-V
Integrated NVIDIA's NVDLA open-source ML accelerator core with a PULP/OpenHW Group RISC-V core. Set up FPGA emulation for the RISC-V subsystem prior to synthesis and place-and-route, and explored IP integration, memory mapping, and connectivity challenges for a streamlined accelerator-based SoC integration.
RTL Verification & Bring-Up Platforms
FPGA-based verification environments for pre-silicon RTL validation of ML accelerator and DSP blocks across all four tape-outs, including stimulus generation, functional coverage, interface emulation, and Python-based post-processing flows for ASIC bring-up support.
FPGA platforms used extensively for pre-silicon verification, bring-up support, and rapid prototyping across all four tape-out projects.
Publications
Experience
PhD Candidate / Digital ASIC Designer
- Defined digital subsystem architectures and microarchitecture specifications for low-power Edge AI SoCs, translating sensing, inference, bandwidth, latency, and power requirements into RTL data paths, control sequencing, interfaces, and validation plans.
- Designed AI-enabled ASIC data paths in 65 nm CMOS, including ML accelerators, DSP/filtering pipelines, adaptive control logic, feature-extraction/classification engines, packetization logic, and top-level SoC integration.
- Owned PPA-aware implementation across 4 tape-outs, spanning architecture/specification, RTL, simulation, synthesis, timing closure support, SoC integration, chip bring-up, and post-silicon validation.
- Collaborated with analog, mixed-signal, and RF teams on AMS simulation, interface timing, clock/reset integration, system validation, and silicon bring-up; contributed to publications at IEEE ISSCC, VLSI, TBioCAS, and BioCAS.
Graduate Teaching Assistant
- Lead TA for ECE1388 (VLSI Design Methodology, Fall 2022–2025) — a graduate course covering end-to-end ASIC design flow from system architecture and RTL through synthesis, physical design, and GDSII generation. Developed a technical user manual for ASIC design tool setup in Linux, delivered 3-hour RTL-to-GDSII tutorials, and mentored students through final projects.
- Led tutorials, labs, office hours, and grading for ECE241 (Digital Systems), ECE253 (Digital and Computer Systems), ECE334 (Digital Circuits), ECE342 (Computer Hardware), ECE212 (Circuit Analysis), and ECE110 (Electrical Fundamentals).
Junior Fellow
- Executive Member of the House Committee and Co-chair of the Community Service Committee.
Product Engineer, Connected Care – NPI
- Contributed to design, development, and release of new service solutions and products for the Patient Monitoring NPI portfolio by reviewing requirements, validating test results, and initiating corrective actions.
- Performed operations audits as lead auditor to ensure compliance to FDA 21CFR820 and ISO13485 regulatory requirements; supported notified body and FDA audits.
- Collaborated with design and systems engineers to ensure products fulfilled 510(k) submission descriptions.
- Led multiple continuous improvement and problem-solving projects across business units with cross-functional teams; received Manager Recognition Awards 9 times.
Graduate Student Researcher
- Developed a wireless telemetry system to record data from a chronically implanted device for real-time neural recording and stimulation in a freely moving rat model.
- Controlled recording and stimulation via BLE; conducted bench testing and acute animal experiments to validate the implant design. Published at IEEE BioCAS 2018.
Product Engineer – Service Innovations Co-op
- Completed design and validation deliverables for the successful launch of the Vereos PET/CT system.
- Contributed to product design, manufacturing, installation, and serviceability with a focus on defect identification and risk mitigation.
Education
PhD, Electrical and Computer Engineering
M.S., Biomedical Engineering
B.Tech, Electronics and Communication Engineering
Technical Skills
RTL & ASIC Design
- Microarchitecture & RTL Design
- Computer Architecture
- DSP / Digital Filtering Pipelines
- ML / AI Accelerator Design
- CPU / NPU Architecture
- SoC / Full-Chip Integration
- Clock Domain Crossing (CDC)
- FIFOs / Data Path Design
- PPA Tradeoff Analysis
- Timing Closure
- Post-Silicon Validation
Languages & Tools
- Verilog / SystemVerilog
- Python
- C / C++
- Tcl / Perl
- Synopsys Design Compiler, PrimeTime
- Cadence Innovus, Xcelium, Virtuoso
- Xilinx/AMD Vivado, Vitis
- Modelsim
ML & Inference
- ML Model Training & Evaluation
- Fixed-Point / Quantized Inference
- SNN / DNN / CNN / Transformer
- Neural Decoding Pipelines
- Edge AI / Real-Time Inference
- Python Validation Flows
Protocols & Platforms
- AXI, APB
- UART, SPI, I2C
- Embedded Linux
- Zynq 7020/7030 SoCs
- PYNQ-Z1, Arty-Z7, Genesys2
- Custom PCB Design
Teaching
Honors & Awards
Service & Volunteering
Blog
Notes on research, digital ASIC design, edge-AI hardware, neural interfaces, and the practical thinking behind technical work. The latest Substack posts are pulled into this section automatically and shown newest first.